Short-wave infrared detector array and method for the manufacturing thereof

ABSTRACT

The invention relates to short-wave infrared (SWIR) detector arrays, and methods for forming such arrays, comprising a light conversion layer (10) having a germanium-tin alloy composition. The shortwave infrared (SWIR) detector array comprises an absorber wafer (II) and a readout wafer (I). The absorber wafer (II) comprises a SWIR conversion layer (10) which has a Gei-xSnxalloy composition. The SWIR conversion layer (10) may have an internal structure comprising an array of rods (12) extending between a patterned support layer (40) and a doped silicon layer (10c). The detector comprises also a readout wafer (I) including an array of charge collecting areas and a readout electric circuit. The readout wafer (I) and the absorber wafer (II) are bonded by a low temperature bonding technique. The invention also relates to methods of fabrication of the SWIR detector array and to SWIR detector array applications such as a multi/hyperspectral LIDAR imaging systems.

TECHNICAL FIELD

The invention relates to short-wave infrared (SWIR) detector arrays fordetection and imaging comprising Complementary Metal Oxide Semiconductor(CMOS) circuits. More precisely the invention relates to the monolithicintegration of a SWIR conversion layer and a CMOS readout circuit and tomethods for realizing such SWIR detector arrays and to applicationsthereof.

STATE OF THE ART

A focal-plane array (FPA) consists of an array of light-sensingpixels—the detector array, attached to a readout circuit (ROIC)—andoperates by detecting photons at particular wavelengths and thengenerating an electrical charge, voltage, or resistance in relation tothe number of photons detected at each pixel. The ROIC converts thecharge collected over time to a voltage through amplification. Thischarge, voltage, or resistance is measured, digitized, and commonly usedto construct an image of the object, scene, or phenomenon that emittedthe photons. FPAs can also be used for non-imaging purposes such aswave-front sensing.

The difficulty in constructing high-quality, high-resolution FPAsderives mainly from the materials used.

The today market-dominating detectors operating in the short-waveinfrared (SWIR)—defined as the wavelength range between 1.0 to 3.0 μm(from the cut-off of Si to that of the mid-wave infrared atmosphericwindow)—rely upon III-V materials (In, Ga, Sb and As) that have theadvantage of high absorption efficiency, high carrier drift velocity andmature design.

Indium Gallium Arsenide (InGaAs) is the preferred material used ininfrared spectroscopy for studying light in the wavelength range of 0.9to 1.6 μm. InGaAs detectors are usually cooled thermoelectrically orcryogenically to extend their spectral range or allow for long exposuredata acquisition. Photoluminescence, Raman spectroscopy, laser diodecharacterization, and fluorescence are among the most common infraredspectroscopy applications that require a high sensitivity detector withlow noise in the SWIR.

Typically, InGaAs arrays are planar structures with p-i-n(positive-intrinsic-negative) or p-n (positive-negative) photodetectorarrays that are monolithic in nature. The detector array has a highbandgap semiconductor (e.g., InP, InAs_(y)P_(1-y,)In_(x)Al_(1-x)As_(y)P_(1-y), etc.) above the In_(x)Ga_(1-x)As tominimize dark current and surface recombination from electron hole pairsthat form in the detector material. The pixel is built by diffusing orimplanting a p-type dopant like Zn, C, or Be into the structure atcertain specific points down to the In_(x)Ga_(1-x)As layer to make thepixel which is a p-i-n or the p-n detector as opposed to doping theentire layer and etching away material to form a mesa structure. Anohmic contact or near ohmic contact is made on top of the diffused areato allow the pixel to be biased and connected to a circuit to remove thecharge collected (both dark charge as well as charge from photons thatare converted to electron hole pairs). A second contact is made (cathodecontact) elsewhere to the n-side material or the substrate, typicallyInP or InAs_(y)P_(1-y,) to allow the circuit to be completed.

HgCdTe is the only common material that can detect in both SWIRatmospheric windows of 1.5 to 1.8 μm and 2.2 to 2.4 μm. Militarytechnology has depended on HgCdTe for night vision. In particular, theUS air force makes extensive use of HgCdTe on all aircraft, and to equipairborne bombs. A variety of heat-seeking missiles are also equippedwith HgCdTe detectors. HgCdTe detector arrays can also be found at mostmajor research telescopes including several satellites. To raise theirsensitivity, they are usually cooled to liquid nitrogen temperature.

In current FPAs, all these materials cannot be used to construct theelectronics needed to transport the resulting charge, voltage, orresistance of each pixel to the measurement circuitry. Therefore, thisset of functions is typically fabricated in silicon using standard CMOSprocesses. The detector array is then hybridized or bonded to the ROIC,typically using indium bump-bonding, such as schematically illustratedin FIG. 1 [Ref. 21]. Different hybridization techniques—direct andindirect—as well as monolithic FPAs with integrated detector and readoutfunctions were successively developed. Another approach known as the“Z-technology” provides extended signal processing real estate for eachpixel by extending the structure in the orthogonal direction. Stackedand thinned readout chips are glued together, and the detector array isconnected to the edge of this signal processing stack with indium.Alternatively, in a “loophole” approach detector elements are connectedto the underlying readout through vias (to allow the charge collection),which are etched through the detector material to contact pads on thereadout part (see http://www.xenics.com/en/infrared-detector-types).Finally, the constraints given by the currently used materials result incomplicated hybridization techniques resulting in low fill factor andsmall overall detection size.

When it comes to selecting a SWIR detector on today market place, thereare four main characteristics that determine the performance of eitherInGaAs or HgCdTe hybridized on a CMOS ROIC: (1) dark current, determinedmainly by bandgap, epitaxy material quality, processing of the diodesand ROIC design; (2) noise is an influential factor, determined by bothphotodiode quality and ROIC; (3) another is readout speed, which isdetermined by the ROIC layout, pixel clock speed and the number ofoutputs; and finally (4) sensitivity, which is determined by materialquantum efficiency (QE) and ROIC amplifier gain.

Not all of these parameters can be optimized at the same time so thatthere are some physical trade-offs involved. State-of-the-art InGaAsoutperforms HgCdTe in terms of dark current, noise and sensitivity. Aswith most infrared materials, InGaAs has to be fabricated on a substratewith the same lattice constant as the alloy itself. Lattice-matchingInGaAs to an indium phosphate (InP) or GaAs substrate normally leads toa cut-off wavelength of 1.6 μm (the most common composition isIn_(0.53)Ga_(0.47)As, lattice matched to InP), while HgCdTe can go up to2.5 μm. The sensitivity of the InGaAs sensor can however be extended byvarying the fraction of indium in the ternary compound that will alsochange the lattice constant of the material. But a higher latticemismatch means also a smaller bandgap and more crystal structuredefects, leading to more dark current and noise, with related highercooling requirements.

Many techniques have been developed to improve InGaAs FPAs. For example,U.S. Pat. No. 6,573,581 describes intentionally doping the intrinsicregion of a p-i-n photodiode to reduce the dark current in planarstructures. U.S. Pat. No. 4,682,196 describes a structure for makinghigh speed, low dark current devices. Known conventional techniques allrequire that the photodiode is directly connected to the amplificationcircuit. The documents U.S. Pat. Nos. 4,904,608 and 5,242,839 describelowering the dark current of mesa detector devices. The documents U.S.Pat. No. 4,656,494 or U.S. Pat. No. 8,039,882 describe avalanchephotodiodes, which have a buried detector layer to allow formultiplication of the charge to occur or for a guard ring to be created.The guard ring is to prevent the gain from spreading beyond theavalanche photodiode. The document U.S. Pat. No. 5,386,128 furtherdescribes a CCD and an InGaAs photodiode integrated into a singleimaging device. The described device moves charge from the photodiode tothe integrated amplification circuit. This device specifically requiresthe photodiode to be directly connected to the amplification circuit anddoes not use a buried photodiode to reduce the dark current. Pinnedphotodiodes are also conventionally used in most modern CMOS imagers.For example, U.S. Pat. No. 6,297,070 discloses a low noise siliconphotodiode that also allows charge transfer enabling correlated doublesampling in the pixel to lower noise.

Other materials for use in the SWIR spectrum were investigated recently.As Si is not suitable and because of the high optical absorption of Geand its compatibility with Si processes, a Ge layer deposition on thetop of Si layer has been investigated. Despite the large latticemismatch (˜4%) between Si and Ge, high-quality Ge thin layer could beachieved with improved fabrication processes, e.g., low-temperaturebonding [Ref. 4], rapid melt growth (RMG) [Ref. 1] and low temperatureepitaxial growth [Ref. 23]. Photodetectors with high performance usingGe-on-Si have also been demonstrated in recent years [Ref. 23, Ref. 14,Ref. 41, Ref. 22]. Among these photodetectors, the avalanche photodiode(APD) emerges as an excellent choice for many applications because ofits internal gain and improved sensitivity [Ref. 23]. As Si shows a verylow k-value (i.e., the ionization ratio of electrons and holes), highlydesirable for APDs to achieve high gain-bandwidth as well as low noise[Ref. 19], Ge-on-Si systems were investigated for developing APDs.CMOS-compatible Ge/Si separate absorption-charge-multiplication SACMAPDs could even be demonstrated [Ref. 23, Ref. 45, Ref. 10]. However, GeAPDs using charge amplification close to avalanche breakdown arecommonly considered to intrinsically suffer from an intolerably highamplification noise.

More recently, GeSn photoconductors on Si were developed andcharacterized [Ref. 8, Ref. 9, Ref. 29, Ref. 11, Ref. 34]. As theincorporation of Sn reduces the difference between the indirect anddirect bandgap in Ge, the pseudo-direct and tunable bandgap ofGe_(1-x)Sn_(x), along with its CMOS compatibility have furthered thedevelopment of this material system that is seen as an attractivesolution for direct incorporation of FPAs with SWIR detection. Somestudies suggest a relaxed Ge_(1-x)Sn_(x) room temperature direct bandgaprequires only 8-9% Sn [Ref. 5, Ref. 18, Ref. 17] whereas the firstdemonstration of lasing using a direct bandgap Ge_(0.874)Sn_(0.126)grown on Si could be reported lately [Ref. 44]. Further advancement ofGe_(1-x)Sn_(x) technology has led to photodetectors that have alreadyshown an extended long wavelength spectral response [Ref. 35, Ref. 25]and an increased responsivity compared to Ge [Ref. 39, Ref. 32].Enhanced long wavelength spectral response out to 2.6 μm was evendemonstrated for a photoconductor with 10% Sn at room temperature [Ref.34]. It means the operation range of GeSn-based optoelectronic devicescan potentially cover all the SWIR wavelengths desirable for Si photonicapplications without the need for a cryogenic cooling system. High speedoperation of Ge_(1-x)Sn_(x) based detectors has also been demonstratedup to 40 GHz opening up the possibility for high speed opticalcommunication [Ref. 32]. In addition, due to the tunable latticeconstant and formation of Lomer dislocations, Ge_(1-x)Sn_(x) has beenshown to work as universal compliant buffer layer to grow high qualitylattice mismatched materials, like III-Vs, on Si [Ref. 2, Ref. 30].However, compared to the photodiodes based on Ge or III-V materials,Ge_(1-x)Sn_(x) photodiode may still suffer from a much larger darkcurrent, which increase the power consumption and degrade thesignal-to-noise-ratio (SNR). In recent studies, the temperaturedependent characteristics and noise mechanisms specific to this materialsystem have been investigated [Ref. 8-9] and provide the baseline for acost effective Ge_(1-x)Sn_(x) FPA integrated on Si for detection in theSWIR spectrum. A surface passivation technique could further be used tosuppress the dark current originating from the mesa sidewall of aGe_(1-x)Sn_(x) on Si p-i-n photodiode [Ref. 12]. It has beendemonstrated elsewhere that the dark current can be reduced either usingSi or yttrium-doped GeO₂ [Ref. 11, Ref. 27] as passivation layer. Adecrease in the device dark current via a thicker GeSn layer may also beachieved that would enhance the absorption in the SWIR [Ref. 34].Finally, owing to the tremendous effort made to develop material growth,including chemical vapor deposition (CVD) and rapid melting growth(RMG), device-level material quality of GeSn could be demonstrated [Ref.30]. Furthermore, an uncooled GeSn detector FPA could be achievedrecently [Ref. 6].

A variety of challenges exists for the growth of GeSn on Si such aslarge lattice mismatch between substrate and alloys (more than 4.2%),low solubility of Sn in Ge and instability of diamond lattice Sn above13° C. In addition to these constraints, the commercial availability ofdeposition gases precursors has to be taken into consideration. The sameapplies to the equipment—including their performance in terms ofoperational lead time and reliability. Out of a summary of reports onGe_(1-x)Sn_(x) growth processes using CVD methods by different researchgroups [Ref. 34], one approach only relies on free available gasprecursors—GeH₄ and SnCl₄—and a commercial reduced pressure (RP)-CVDreactor type [Ref. 28]. A Ge buffer is deposited between the Sisubstrate and the Ge_(1-x)Sn_(x) layer in order to compensate thelattice mismatch between the layers. In another approach, the directgrowth of Ge_(1-x)Sn_(x) films on Si using a cold-wall ultra-high vacuum(UHV) CVD system operates with the same gas precursors, but doesn'trequire a Ge buffer layer [Ref. 29]. The alloy structure is grownstrain-relaxed enabling this material to be a universal compliantbuffer.

Current CVD however show some drawbacks that limit their commercial use.Firstly, they can only achieve a low rate of rate of deposition and athin absorption structure. By UHV-CVD, the growth rate—reliable andefficient enough for industrial use —is extremely low, i.e. for Si inthe order of 3 Å/min at 550° C. (U.S. Pat. No. 6.454.855 B1). Secondly,defects at the growth interface lead to dark conductivity of thestructure. It means threading dislocations, layer cracking and waferbowing—due to lattice and thermally mismatched layers—limit materialschoice, detector size and layer thickness (WO 2011/135432 A1). However,recent growth studies of GeSn and SiGeSn alloys on 200 mm Si(100) and Gevirtual substrates performed in a cold-wall reduced-pressure chemicalvapor deposition (RP-CVD) tool at Peter Grünberg Institute 9 in Jülich[Ref. 44] demonstrate the feasibility of achieving relatively largethicknesses for efficient optical mode confinement. It means up to 1 μmthick GeSn layers with Sn contents up to 14% were grown on thick relaxedGe buffers, using Ge₂H₆ and SnCl₄ precursors and a strong strainrelaxation (up to 81%) at 12.5% Sn concentration could be obtainedwithout crystalline structure degradation [Ref. 42].

In a comprehensive list of Ge epitaxy methods [Ref. 43], a new procedurebased on low energy plasma-enhanced CVD (LEPECVD) emerges [Ref. 33]allowing for low threading dislocation density under low thermal budgetand much higher deposition rates in comparison with the UHV-CVD method.By PECVD with DC discharge, growth rates of at least 150 Å/min or even600 Å/min may be achieved. Using this procedure, a near-infrared imagersensor with monolithically integrated Ge photodiodes has beendemonstrated that has sufficiently low dark current for camera operationwith moderate Peltier cooling [Ref. 24]. A sufficient thickness of theGe crystal rods could be achieved [Ref. 13] which can be considered as ascientific breakthrough as normally the strain introduced by growing asingle crystalline layer of one material on a second crystal differingin lattice parameter can persist only up to a certain criticalthickness. However, as previously mentioned, substantially pure Ge isconsidered to intrinsically suffer from an intolerably highamplification noise. Furthermore, pure Ge has a cut-off wavelength of1.6 μm, limiting its potential field of applications in the SWIR.

SUMMARY OF THE INVENTION

It is the aim of this invention to provide a short-wave infrared (SWIR)focal plane array (FPA) with improved performance in comparison withinfrared detector arrays of prior art. This SWIR detector arraycomprises a monolithic avalanche photodiode layer stack structure whichhas a small size and a small weight. Furthermore the detector array ofthe invention has a large sensitivity and comprises a large area FPAallowing covering efficiently the whole SWIR spectrum atroom-temperature or eventually Peltier-cooled operation. The large areaFPA provided by the invention are furthermore advantageous over tilingmultiple smaller FPAs and result for example in a substantially completesurface coverage, compared to FPAs of prior art which have gaps betweenthe tiled arrays.

More precisely the SWIR FPA of the invention comprises a SWIR conversionlayer having a free surface forming an incident light surface of thedetector array. The SWIR detector array comprises also a doped readoutwafer being either a p-doped or n-doped. The readout wafer comprises:

-   -   an array of charge collecting areas being either p-doped or        n-doped charge collecting areas;    -   a readout layer comprising an electrical circuit and defining a        detector lower surface opposite the incident light surface, said        SWIR detector array being configured to detect electromagnetic        waves having a wavelength comprised between 1.0 μm and 3.0 μm.

The SWIR detector array further comprises a support layer to itsincident light side, said support layer comprising silicon and beingeither p-doped or n-doped, the doping of said support layer beingdifferent with respect to the doping of said doped readout wafer.

The SWIR detector array further comprises an intermediate layercomprising a p-n junction and a bonding interface 1 c-1 d, saidintermediate layer being arranged in between said support layer and saidreadout wafer.

The SWIR light conversion layer has a Ge_(1-x)Sn_(x) alloy compositionand comprises, to the side away from said intermediate layer a dopedcontact layer having a similar doping as said support layer, said dopedcontact layer being covered by an electrical contact layer.

In an embodiment the layer stack comprises said intermediate layer, astrain-relaxed Ge buffer layer, a Ge_(1-x)Sn_(x) alloy SWIR conversionlayer and a doped Ge contact layer deposited on said SWIR conversionlayer as described further under the fabrication steps b2′-b4′.

In an embodiment said p-n junction is situated to the side of saidsupport layer.

In an embodiment said p-n junction is situated to the side of saidreadout layer.

In an embodiment said p-n junction comprises said bonding interface andhaving a first portion situated to the side of said support layer and asecond portion situated to the side of said readout layer.

In an embodiment said readout electrical circuit is a CMOS type circuitprocessed in said readout layer so as to be accessible in said detectorlower surface.

In an embodiment said light conversion layer has a thickness t1, definedin a direction perpendicular to said support layer of more than 350 nm,preferably more than 1 μm, still preferably more than 10 μm.

In an embodiment said support layer is a patterned layer and comprisestrenches and elevated regions to its incident light side.

In an embodiment said SWIR light conversion layer is internallystructured and comprises rods extending between said support layer andsaid doped contact layer. An advantage of said rods grown on a latticeand thermally mismatched substrates is that it reduces threadingdislocation effects and so enhances the charge collection efficiency ofthe detector.

In an embodiment said rods have, defined in any cross sectionperpendicular to their length L, a <100>crystallographic orientation.

In an embodiment a greatest width of said rods, taken in any said crosssection, is comprised between 1 μm and 7 μm.

In an embodiment said contact layer is a patterned contact layer.

In an embodiment the conversion efficiency is higher than 30%,preferably higher than 60%.

In an embodiment said absorption layer is realized by a LEPECVDtechnique.

In an embodiment to the incident light side, an optical layer is adaptedto the incident light side of said rods to direct incident light intosaid rods.

In an embodiment said optical layer comprises an array of refractivemicrolens, or an array of diffractive microlenses, or an array ofaspheric shaped microlenses, or an array of microprisms or an array ofplasmonic planar metalenses allowing for multi/hyper-spectral imagingand analysis.

The invention is also achieved by a method of fabrication of a SWIR FPAand comprises the steps of:

-   -   a) Fabrication of a readout wafer comprising the steps (a1-a7)        of:        -   a1) providing a first silicon wafer being a low doped p or n            type SOI wafer comprising a readout layer;        -   a2) forming a readout circuit in said readout layer by a            Complementary Metal Oxide Semiconductor (CMOS) process;        -   a3) realizing charge collecting areas in said readout layer,            said charge collecting areas being n-doped or p-doped with            the same doping kind as the SOI wafer;        -   a4) planarizing said first silicon wafer to the same side of            readout layer;        -   a5) adapting a readout carrier layer to said silicon wafer            to the side of said readout layer by low temperature            oxide-to-oxide bonding;        -   a6) thinning said first silicon wafer by conventional            grinding and plasma etching techniques;        -   a7) providing a smooth, clean and oxide-free bonding surface            by chemical polishing and passivation, so as to provide said            readout wafer.    -   b) Fabrication of an absorbing wafer comprising the steps        (b1-b9) of:        -   b1) providing a second silicon layer having either a p-type            doping or n-type doping opposite to the doping of said            charge collecting areas;        -   b2) patterning and passivating the surface of said second            silicon layer so as to form a support layer comprising            trenches and elevated regions;        -   b3) depositing, by a LEPECVD process, a SWIR conversion            layer made of an Ge_(1-x)Sn_(x) alloy composition with a Sn            content x between 0.04 ≤x≤0.15 and so that during the            deposition process rods are formed having a composition of            Ge_(1-x)Sn_(x), said rods having a basis situated on said            elevated regions and having a length L being at least a            portion of the thickness t1 of said SWIR light conversion            layer, said rods having a top surface opposite to said            bottom surface;        -   b4) passivating the surface of the rods and filling the gaps            between said rods;        -   b5) planarizing the upper surface of the rods;        -   b6) providing by low temperature oxide bonding an absorber            carrier wafer on top of the planarized upper surface;        -   b7) thinning, to a predetermined thickness t2, the formed            stack comprising the patterned support layer and said SWIR            light conversion layer so as to form said absorber wafer;        -   b8) providing to said absorber wafer, a smooth, clean and            oxide-free bonding surface to the side opposite of said            upper surface by conventional surface techniques such as            chemical mechanical polishing and wet chemical cleaning.    -   c) covalently bonding both surfaces so as to form a bonding        interface and so that the SWIR detector array comprises an        absorber wafer bonded to said readout wafer, forming a        monolithic detector array unit;    -   d) annealing the monolithic detector array unit to realize        hydrogen diffusion across the bonding interface, the annealing        being performed by annealing temperatures lower than 350° C.;    -   e) removing the absorber carrier wafer by conventional etching        techniques;    -   f) depositing on said SWIR light conversion layer, to the side        away from said readout wafer I a doped layer having a doping of        the type of said support layer;    -   g) forming electrical contacts on top of said doped layer;    -   h) removing the readout carrier by conventional etching        techniques;    -   i) opening contacts to the readout electronics by        photolithography and dry etching;    -   j) forming a patterned or non patterned electrical contact        layer.

In an embodiment an optical incoupling layer is provided on top of saidpatterned electrical contact layer.

In another embodiment the fabrication steps (b1-b7) of the absorber arereplaced by the following steps (b1′-b7′):

-   -   b1′) providing a second clean and oxide-free SOI substrate wafer        having either a p-type doping or n-type doping opposite to the        doping of said charge collecting areas;    -   b2′) depositing by a RP-CVD process a Ge buffer layer on said        second silicon wafer;    -   b3′) depositing, by a RP-CVD process, a SWIR conversion layer        made of an Ge_(1-x)Sn_(x) alloy composition with a Sn content x        between 0.04 ≤x≤0.15;    -   b4′) forming a Ge contact layer by RP-CVD and doping;    -   b5′) providing by low temperature oxide bonding a carrier wafer        on top of the planarized upper surface;    -   b6′) thinning, to a predetermined thickness t2, the formed stack        comprising said patterned layer and said SWIR light conversion        layer so as to form said absorber wafer;

b7′) providing to said absorber wafer, a smooth, clean and oxide-freebonding surface to the side opposite of said upper surface byconventional surface techniques such as chemical mechanical polishingand wet chemical cleaning.

In an embodiment the passivation of the bonding surface is performed bya low energy hydrogen implantation technique.

In an embodiment a doped layer is realized in said absorber wafer to theside of said bonding surface, said doped layer having the samedoping-type as the charge collecting areas to provide a p-n junctionwithin the SWIR absorber.

In an embodiment said SWIR light conversion layer, is doped to the sideaway from said support layer, so as to form a doped layer having adoping of the type of said support layer.

In an embodiment a doped layer is realized in said readout wafer, to theside away from said readout layer. This doped layer having an oppositedoping-type as the charge collecting areas so as to provide a p-njunction within the CMOS wafer.

In an embodiment in step c) said covalent bonding is realized by a lowtemperature bonding technique, said low temperature being lower than300° C.

The invention is also achieved by an optical system comprising said SWIRdetector array and arranged to operate in a single-photon counting mode.

In an embodiment said SWIR detector array is part of a high sensitiveLIDAR.

These and other objects of the invention are described in the drawings,specifications and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details of the invention will appear more clearly upon readingthe following description in reference to the appended figures:

FIG. 1 illustrates a cross-section of a hybrid detector array of priorart having an absorber layer and a readout layer connected bybump-bonding;

FIG. 2a illustrates a schematic cross-section of the SWIR photodiodestructure of the invention;

FIG. 2b illustrates a schematic cross-section of the SWIR photodiodestructure wherein the SWIR absorption layer comprises an array of rods;

FIGS. 3a-b illustrates two different cross-sections of the SWIR absorberlayer;

FIG. 4 illustrates a detailed structure in the SWIR conversion layercomprising rods separated by gaps:

FIG. 5 illustrates a preferred embodiment of the invention comprising anavalanche layer stack configuration base on a n⁺ layer, a p layer and ap⁺ layer;

FIGS. 6a-c illustrates different alignment configurations of rodsrelative to a charge collection area of a readout layer;

FIG. 7a illustrates a layer stack comprising a patterned layer, a SWIRconversion layer, a doped contact layer and a patterned electricalcontact layer;

FIG. 7b illustrates a first silicon wafer comprising a readout layercomprising charge collectors and a readout electrical circuit;

FIG. 8 illustrates an embodiment of the p-i-n diode structure of theSWIR FPA;

FIG. 9 illustrates an optical layer arranged to couple SWIR light intothe rods of a SWIR light conversion layer.

EMBODIMENTS OF THE INVENTION

FIG. 1 illustrates a SWIR detector array 1 of prior art. As described inthe prior art such a detector array comprises typically a microlensarray (A) and an absorber sheet typically made of InGaAs (B), as well asa readout circuit realized on a separate layer or wafer. The stackcomprising the optical layer (A) and the absorber layer (B) iselectrically and mechanically connected to the CMOS layer (C) by anarray of bumps. The hybrid assembly of prior art infrared detectorarrays, as illustrated in FIG. 1, requires a complex and delicatealignment process and does not allow to provide large, cheap, reliableand high efficient SWIR detector arrays.

FIG. 2a and FIG. 2b illustrate two embodiments of the invention. It isunderstood that all FIGS. 2-8 only illustrate cross sections of aportion of the complete detector array 1. Compared to infrared detectorsof prior art, the device of the invention provides a highly efficientmonolithic SWIR detector array 1 comprising a simplified and wide layerstack structure having a small thickness, a reduced weight and lowerpower requirements. The SWIR detector array 1 of the invention is alsocalled a focal plane array (FPA) hereafter. The device of the inventionallows to provide very sensitive and large area monolithic FPAs able tocover efficiently the whole SWIR spectrum at room-temperature oreventually Peltier-cooled operation. Said SWIR spectrum is defined by awavelengths range between 1.0 μm and 3.0 μm.

The FPA 1 of the invention is configured to detect electromagnetic waveshaving a wavelength comprised between 1.0 μm and 3.0 μm.

In an embodiment of the invention, illustrated in FIG. 2 a, the SWIRdetector array 1 comprises the following elements:

-   -   a) a doped contact layer 10 c;    -   b) a SWIR conversion layer 10, also defined as absorption layer        or light conversion layer, having a free surface forming an        incident light surface 1 a of the detector array 1, said        conversion layer is arranged for converting short wavelength        infrared photons in electron-hole pairs. The SWIR conversion        layer 10 has a Ge_(1-x)Sn_(x) alloy composition.    -   c) a support layer 40 comprising silicon and being either        p-doped or n-doped, the doping of said support layer 40 being        the same as said doped contact layer 10 c and opposite to the        doping of the electric charge collectors in the CMOS readout        layer 20;    -   d) an intermediary stack layer 30 comprising a p-n junction and        a bonded interface 1 c-1 d between the SWIR absorber wafer and        the readout wafer,    -   e) a readout wafer 20 comprising the COMS readout circuits 22,        including electric charge collectors 24.

In an embodiment the layer stack comprises said intermediate layer, astrain-relaxed Ge buffer layer, a Ge_(1-x)Sn_(x) alloy SWIR conversionlayer and a doped Ge contact layer deposited on said SWIR conversionlayer as described further in the fabrication steps b2′-b4′.

In another embodiment the FPA 1 of the invention, illustrated in FIG. 2b, the SWIR detector array 1 comprises the following elements:

-   -   a) a doped contact layer 10 c;    -   b) a SWIR conversion layer 10, also defined as absorption layer        or light conversion layer, having a free surface forming an        incident light surface 1 a of the detector array 1, said        conversion layer is arranged for converting short wavelength        infrared photons in electron-hole pairs; the SWIR conversion        layer 10 has a Ge_(1-x)Sn_(x) alloy composition and is, in this        embodiment, internally structured such that it comprises rods 12        extending between said patterned layer 40 and said doped layer        10 c having a similar doping as the patterned layer 40;    -   c) a support layer 40 being a patterned layer comprising        trenches 42 and elevated regions 44 to its incident light side,        said support layer 40 comprises silicon and is either p-doped or        n-doped, the doping of said support layer 40 is the same as said        doped contact layer 10 c and opposite to the doping of the        electric charge collectors in the CMOS readout layer 20;    -   d) an intermediary stack layer 30 comprising a p-n junction and        a bonded interface 1 c-1 d between the SWIR absorber wafer and        the readout wafer;    -   e) a readout wafer 20 comprising the COMS readout circuits 22,        including electric charge collectors 24.

It is understood that in the embodiment of FIG. 2b wherein the SWIRconversion layer 10 comprises rods, the support layer 40 is a patternedlayer and that in the case of the embodiment of FIG. 2 a, the supportlayer 40 is a substantially smooth layer 40.

It is also understood that said intermediate stack layer 30 may bearranged to the side of the absorber layer. In a variant a firstintermediate stack layer 30 may be arranged to the side of said readoutwafer 20 and a second intermediate stack layer 32 to the side of saidabsorber wafer as illustrated in the embodiment of FIG. 7a -b.

In all the embodiments of the invention said p-n junction may besituated to one of the sides of said bonded interface 1 c-1 d or maycomprise a first portion to one side of said bonded interface 1 c-1 dand a second portion to the other side. Said bonded interface must notbe necessarily in the middle of said p-n junction.

The stacked layer configuration comprising said SWIR conversion layer10, said support layer 40, said intermediate stack 30, which is inelectrical connection with said electric circuit 22 and the furtherdescribed electrical contact layer 50, forms a SWIR avalanchephotodetector array (APD) configuration. The array configuration of thedetector 1 of the invention is formed by the electrical connectionbetween the absorbing layer 10 and the array configuration of theelectric charge collecting regions 24 as further described.

The rods 12 are grown by a low temperature epitaxial process, asdescribed further, so that they have a well-defined crystallographicstructure and present reduced defects, such as threading dislocations atthe interface between the seed patterned layer 40 and the grown rods 12.Growing Ge_(1-x)Sn_(x) alloy rods with an Sn content x between about0.04≤x≤0.15 on a support layer 40 allows also providing a structuredabsorption layer 10 rather than a continuous film, which provides,besides the extension of the absorption edge to longer wavelengthcompared with Ge, a detector device with higher performance thanks tolow threading dislocation defects between lattice mismatched materials,the lower thermal sensitivity, a less stringent demand on temperaturestability compared with the conventional III-V based photodetectors[Ref. 11] and a large responsivity at low power over the whole SWIRwavelength range. Depending on the alloy composition and the targetedquantum efficiency, the absorber material thickness t1 may be as thin as10.0 μm to 20.0 μm or even 0.5 μm to 10.0 μm. The absorption layer 10 isrealized preferably by a LEPECVD technique as explained further.

As illustrated in FIGS. 3a-b said rods 12 are preferably formed, asfurther described in the section related to the fabrication method, onsaid elevated regions 44 but may also be formed on said trenches 42.Said rods 12 define a rod basis 12 a on the support layer 40 and anupper surface 12 b opposite to said basis 12 a. Said trenches 42 and/orsaid elevated regions 44 may comprise microstructures or additionallayers to limit defects during the formation of said rods.

Adjacent rods 12 are separated by gaps 14 as illustrated in FIG. 4.These gaps 14 may be filled with a passivation layer. This passivationlayer may be a dielectric passivation layer and may be formed during orafter the growth process of the rods 12.

Said gaps 14 may be filled with a material suitable to improve theconfinement of infrared light into said rods 12, or may be suited toreduce the leakage of infrared light and/or electrical charges outsidesaid rods 12. Said rods 12 may be arranged as an closely packed rodarrays, for example an array comprising substantially hexagonal shapedrods 12 that have at least one lateral face in contact with at least aportion of a face of a neighboring rod 12.

It is understood that the width of the gaps 14 between the rods 12 maybe as small as allowed by the lithography and deep reactive ion etchingtechniques known in the art. For example the width of the gaps 14 may belower than 1 μm, or below 500 nm or even below 100 nm.

A wide variety of packing densities and packing configurations arepossible. For example, as illustrated in FIG. 6a-c each chargecollecting area 24 of the readout wafer 20 may face a predeterminednumber of rods 12.

In a variant, illustrated in FIG. 6a a single rod 12 has its basis 12 afacing a single charge collecting area 24. As illustrated in thevariants of FIG. 6b and FIG. 6c a bundle of rods 12 may face a singlecharge collecting area 24. Preferably said rods 12 have an orientationperpendicular to the plane of said support layer 40, but they may have apredetermined angle relative to the support layer 40. The cross sectionof said rods 12 may have any shape and their shape may vary according totheir position in the array of rods 12. For example the shape of a crosssection of said rods 12, defined perpendicular to its length L, may besubstantially hexagonal, rectangular, or circular.

In a variant illustrated in FIG. 6b the rods 12 may have a conicalshape. The conical shape may be so that its largest cross section issituated at the upper surface 12 a so as to enhance the internal angleof reflection on the side wall of the rods. It is also understood thatthe array of rods 12 may comprise different shaped rods 12 and maycomprise a portion of rods 12 that have a different chemicalcomposition. In some applications of the device the central portion ofthe array of rods, defined in the plane of said array of rods 12, mayhave a different chemical composition than the rods 12 situated at theoutside border portion of the array of rods 12.

It is understood that the packing density of the array of rods 12 may bedifferent in different portions of said array of rods 12.

Said rod basis 12 a may be equal to or may be smaller or greater thansaid upper surface 12 a. A rod 12 may have for example a widecylindrical portion to the side of said rod basis 12 a and may have athinner cylindrical portion to the side of said upper surface 12 b.Also, the shape of the rods 12 may vary according to their position inthe array of rods 12.

It is also understood that the chemical composition of at least aportion of the rods may vary from its basis 12 a up to its upper surface12 b. For example, a first portion of a rod 12, to the side of its basis12 a, may have a higher Sn content than a second portion to said rod toits upper surface 12 b. The rods may comprise, in its length, a step inthe concentration of Sn. The Sn concentration may also be a continuousgradient along the length of the rods.

It is also understood that said rods 12 may have a radial indexdistribution, similar to graded index fiber optics. This radial indexdistribution may be realized by specific dopants and/or by a radialdistribution of the Sn concentration.

It is understood that said rods 12 may comprise a variety of dopants.For example, a p-type layer may be formed by BF₂ ⁺ ion implantation[Ref. 11]. Boron via B₂H₆ may also be a candidate of choice [Ref. 28].For an n-type layer, phosphorous (via PH3) will be preferred.

Preferred sizes of said rods 12 are:

-   -   length: preferably between 1 μm and 20 μm;    -   largest cross section: preferably between 1 μm and 5 μm.

It is generally understood that the width of said trenches 42 and/orsaid elevated regions 44 are preferably chosen in accordance with thethermal mismatch in order to reduce at most the formation of thermalcracks during the bonding process or during a post-bonding anneal.

The rods 12 are configured to convert an incident photon into anelectron-hole pair and have an infrared light guiding function at leastto their incident light side. The array of rods 12 in the SWIRconversion layer 10 allows for improved properties compared to a lightconversion layer that would be made of a continuous layer.

In an embodiment, illustrated in FIG. 7 a, said doped layer 10 c iscovered by an electrical contact layer 50. In a variant said doped layer10 c may be formed by doping the incident light side of thephoto-conversion layer 10. In a variant this doped layer is deposited tothe incident light side of the photo-conversion layer 10.

Said electrical contact layer 50 is preferably a patterned electricalcontact layer 50.

In a variant said doped layer 10 c may comprise a patterned electricalcontact layer. In a variant said doped layer 10 c is said patternedelectrical contact layer 50.

The patterned electrical contact layer 50 may be a patterned metal layeror a patterned conducting layer made of a non-metallic material such asZnO. Said contact layer 50 may be any electrical conductingsemiconductor layer 50 which is transparent to SWIR.

In an embodiment said intermediate silicon layer 30 comprises a p-njunction. In an embodiment said intermediate layer 30 comprises aslightly doped layer adjacent to the support layer 40 having the samedoping type and another slightly doped layer of opposite type adjacentto silicon wafer 20. In a variant the absorber layer 10 may be a dopedlayer.

In a preferred embodiment said intermediate silicon layer 30 comprisesthe bonding interface 1 c-1 d and is situated between the SIWR absorber10 and the readout wafer. This bonding interface 1 c-1 d may be at oneor the other side of the layer, and in any place in-between. Thisbonding interface may be situated to one of both sides of p-n junction.

It is understood that in all embodiments of the invention the shapeand/or the surface of said rods 12 may be configured so as to optimizethe electrical field in the length and across of said rods. Also, saidgaps 14 may comprise materials and/or structures which allow, inoperation of the detector array 1, to confine the electrical field linesinside said rods 12.

A preferred embodiment of the detector 1 of the invention is illustratedin FIG. 5. In the embodiment of FIG. 5 the silicon layer 20 comprises n+charge collectors 24, whereas the support layer 40 is a p-doped layerand said doped layer 10 c is a highly p-doped layer. In the preferredembodiment of FIG. 5 said absorption layer 10 is non-doped. In a variantof said preferred embodiment said absorption layer 10 may be a dopedlayer. As illustrated in FIG. 5 a photon incident on the absorptionlayer 10 creates an electron-hole pair in the absorber 10. The hole iscollected at the incident light side and the electron, created by theabsorption of a photon, drifts to the multiplier region situated to theside of said charge collectors of the p-n junction and is accelerated tosufficient energy to initiate a chain of impact ionization events,creating offspring electron-hole pairs and leading to internal gain. Inthe Geiger mode, in which single photon can initiate an avalanche thatis self-sustaining, carrier generation predominates over extractionleading to exponential growth of the current. In this mode the detectorarray has to be electrically reset by reducing the bias to belowbreakdown long enough to terminate the avalanche, a process known asquenching.

In a variant the avalanche photodiode (APD) structure of the detectorarray 1 may comprise further layers such as buffer layers and/or chargelayers. Depending on the desired electrical performances of the detectorarray 1 the layers of the APD structure of the detector 1 may beconfigured so as to shape a predetermined electrical field profileacross the APD structure of the detector. Shaping electrical fieldprofiles is well known in the field of designing APDs and are notfurther commented here.

The pixelated configuration of the SWIR detector array of the inventionis described hereafter.

The SWIR detector array comprises two basic layers I and II, asillustrated in a preferred embodiment of FIGS. 7a -b, which show anexample of a portion of the SWIR detector 1. A first layer, illustratedin FIG. 7 b, defined as the absorption wafer II comprises at least onesupport layer 40 which may be a patterned layer 40, an absorption layer10, a doped layer 10 c and an electrical contact layer 50. By an etchingtechnique, said absorption wafer II has a predetermined thickness t1+t2and has a bonding surface 1 c situated opposite said patternedelectrical contact layer 50. Said predetermined thickness is preferablybetween 20 μm and 40 μm, more preferably between 10 μm and 20 μm.

Another wafer I, illustrated in FIG. 7 b, comprises the readout wafer 20which includes a diffusion layer 20 b and a readout layer 20 c. In anembodiment wherein the p-n junction should be situated within thisreadout wafer I, a layer of a different doping type 30 is realizedadjacent to the diffusion layer 20 b. The readout layer 20 c comprisesan electrical circuit 22 which comprises charge collecting areas 24 anda readout electronic circuit. This readout electronic circuit comprisestransistors and doped areas such as p- or n-wells. Said charge collectorareas 24 are preferably n implants or p implants. The distance betweentwo charge collecting areas 24 defines the pitch of the detector array.Typical values of that pitch may range for example from 5 μm-10 μm or 10μm-50 μm, depending on the CMOS process used.

In a preferred embodiment, illustrated in FIG. 8 which shows only aportion of the detector 1, the charge collectors are n-implant regions24. In the embodiment of FIG. 8 the p-side of the avalanche stack istied to a negative bias voltage slightly less in magnitude than thebreakdown voltage and the charges that are collected are electronsprovided by electron-hole pairs which are generated by the incidence ofphotons on absorber layer 10 and which are separated by the n-pconfiguration in the intermediate layer 30 between the patterned layer40 of the absorbing wafer II and the readout wafer I. The distancebetween said charge collecting areas 24 define the pixel size of thedetector array 1. The pixel size that can also be defined by thedistance between adjacent n-wells, may range for example from 5 μm-10 μmor 10 μm-50 μm, depending on the CMOS process used, allowing for asuperior spatial resolution in comparison with devices of the prior art.

In order to allow for efficient charge collection, the readout wafer 20should preferably be thin such that the space charge region, inoperation of the device, extends mainly through said absorption layer10. The thickness of said readout wafer 20 is preferably smaller than100 μm, more preferably smaller than 50 μm, and more preferably below 40μm.

The readout layer 20 c in the preferred embodiment of FIG. 8 comprisespixel electronics such as n-MOS (T1) and p-MOS transistors (T2) that arerespectively situated in p-wells 23 and n-wells 25. In such a case thereadout layer 20 c comprises preferably also deep p-wells 27 facing thetransistor n-wells 25 to avoid that these n-wells 25 collect electronsin addition to the charge collecting n-wells 24.

Designing p and n well charge collectors 24 and deep n or p wells inCMOS charge collecting and readout electronic circuits and theirprocesses, such as those using SOI wafers hosting such circuits, arewell known to the person skilled in the art and are not furthercommented here.

In an embodiment said readout electrical circuit 22 is a CMOS typecircuit processed in said readout layer 20 c so as to be accessible insaid detector lower surface 1 b. In an embodiment the readout wafer 20is preferably processed in an epitaxial thin Si layer and has aresistivity according to a low doping level in between about 10¹¹ to10¹³ cm⁻³ of a first conduction type (for example n-conduction inducedby n-doping), whereas the conduction type of the second layer II, alsodefined as absorption wafer II, should be opposite to that of thereadout wafer I, for example p-conduction when the readout wafer I isn-doped. Depending on the alloy composition, the absorption layer 10 maybe as thin as 10.0 μm to 20.0 μm or even 1.0 μm to 10.0 μm to provide ahigh quantum efficiency of the detector array 1.

Said second layer II is electrically and mechanically connected, bybonding, to said bonding surface 1 d of said first layer I so as to forma monolithic detector structure which does not comprise any gaps orvoids between the layers I and II. This is preferably achieved by a lowtemperature bonding technique as described in detail further in thefabrication method section.

Unlike the complex hybridization techniques of the infrared detectors ofprior art, requiring transfer and bump bonding, the invention makes useof a low-temperature direct covalent wafer bonding method, whereby aCMOS processed readout electronics and a sensor wafer are combined in adetector structure forming a monolithic unit.

Efficient charge collection across the bonded interfaces is enabled bythe following processing steps, further described in the fabricationprocess flow described in a separate section:

-   -   surface preparation techniques providing smooth, clean and        oxide-freesurfaces;    -   low energy implantation of hydrogen in the range from 20 eV to        20 keV;    -   wafer bonding equipment including a He plasma source, and    -   post-bonding anneal for the hydrogen diffusion towards the        bonding interface.

It is generally understood that different embodiments of the absorberwafer II may be devised, such as variants to the embodiments of FIGS. 2aand 2b and that the realization of said readout wafer I and its bondingto said absorber wafer II may be adapted in function of the nature andthe structure of said absorber wafer II.

The SWIR detector array 1 of the invention allows to obtain a high SWIRconversion efficiency, defined as the ratio of the number ofelectron-hole pairs generated to the number of incident photons in saidabsorber layer II. In an embodiment the conversion efficiency is higherthan 30%, preferably higher than 60%.

The FPA 1 of the invention may have a large lateral dimension of about10×10 cm² for one tile or even 50×50 cm² by stitching tiles—or any otherjuxtaposition technique.

It is understood that the detector array 1 of the invention may beconfigured in different electrical operational modes. More precisely byconstruction, the monolithic FPA of the invention may be designed inorder to either time stamp photons or count them. It means that eachphoton arrival is digitally recorded by the activated pixel circuit. Themonolithic FPA of the invention is therefore suitable also for energydiscrimination, whereby the energy of photons incident on the sensor canbe analyzed by the electronic circuit 22. Because digitization occurswithin the pixels of the detector array, there is no need for analogcircuitry in the readout path, and therefore this photon countingfeature in the FPA of the invention eliminates readout noise. Thus, thesingle-photon counting highly sensitive SWIR FPA offers a reliablesolution to avoid collisions of unmanned—aerial or terrestrial—vehicle.

The FPA of the invention comprising an array of single-photon avalanchediodes (SPAD) may further operate at room-temperature or eventuallyPeltier-cooled operation.

It is understood that the readout electronics of the detector 1 may bearranged to convert electrical signals into digital signals which can bestored and/or processed and that said digital signals may be furtherdisplayed as images on a computer screen.

Referring now to FIG. 9, an optical layer 100 may be adapted to thedetector array 1 to deviate incident sideways radiation 200, so that thelight incoupling of light rays 202 coupled inside the rods is improved,and so as to improve the light guiding efficiency of the rods 12, whichenhances the light absorption of incident photons on said rods 12.Different variants of said optical layer 100 are possible. For examplesaid optical layer 100 may comprise: refractive microlens, diffractivemicrolens array, aspheric shaped microlens arrays, microprism arrays.The optical layer may also comprise plasmonic planar metalenses allowingmulti/hyper-spectral imaging and analysis. It is understood that saidoptical layer may comprise a stack of optical layers and may compriseoptical shutters such as an array of electrostatically driven microshutters, such as mems silicon micro shutters, which may be used toimprove detection performances of optical systems in which the detectorarray 1 is implemented.

Referring now to the fabrication process flow, the key steps tomanufacture the SWIR detector are described below.

The fabrication process comprises three main steps a), b), and c):

-   -   a) Realizing a readout wafer I;    -   b) Realizing an absorbing wafer II;    -   c) Bonding of the readout wafers I and the absorbing wafer II.    -   These three steps a), b), c) are described in detail hereafter:

a) Realizing a Readout Wafer (I)

In an embodiment the realization of the readout wafer I comprises thefollowing steps (a1-a8):

-   -   a1) providing a first silicon wafer being a low doped SOI wafer        comprising a readout layer 20 c;    -   a2) forming, in said readout layer 20 c a readout circuit 22 by        a Complementary Metal Oxide Semiconductor (CMOS) process; the        SOI wafer may be a high resistivity p or n type doped wafer;    -   a3) realizing charge collecting areas 24 in said readout layer        20 c, said charge collecting areas 24 being n-doped or p-doped        with the same doping kind as the SOI wafer;    -   a4) planarizing said first silicon wafer 20 to the side of the        CMOS readout layer 20 c by depositing oxide and        chemical-mechanical polishing;    -   a5) adapting a first carrier layer, defined as readout carrier        layer, to said silicon wafer 20 on side to the CMOS by low        temperature oxide-to-oxide bonding;    -   a6) thinning said first silicon wafer 20 by conventional        grinding and plasma etching techniques;    -   a7) providing a smooth, clean and oxide-free bonding surface 1 d        by chemical mechanical polishing and passivating the surface 1 d        by a low energy hydrogen implantation in the range of 20 eV to        20 keV, as known in the art for plasma cleaning of silicon        wafers to diffuse to the bonded interface and passivate dangling        bonds.

b) Realizing an Absorbing Wafer (II)

In an embodiment, the realization of the absorbing wafer II comprisesthe steps (b1-b8):

-   -   b1) providing a second SOI substrate wafer having either a        p-type doping or n-type doping opposite to the doping of said        charge collecting areas 24;    -   b2) patterning and passivating the surface of said second        silicon wafer so as to form said support layer 40 comprising        trenches 42 and elevated regions 44; the trenches—created by        photolithography and dry reactive ion etching—as well as the        width of the top surfaces may range between 2 and 6 μm. To        reduce the lattice mismatch between GeSn and silicon, a thin        undoped Ge buffer layer may optionally be deposited prior to the        patterning;    -   b3) depositing, by a LEPECVD process a SWIR conversion layer 10;        in order to get a sufficient thickness and a structure with low        threading dislocation defects, said process able to process free        available gas precursors such as GeH₄ and SnCl₄, on said support        layer 40 a nominally undoped (intrinsic) but conducting or        lightly doped SWIR conversion layer 10 made of an Ge_(1-x)Sn_(x)        alloy composition with a Sn content x between 0.04≤x≤0.15 and so        that during the deposition process rods 12 are formed having a        composition of Ge_(1-x)Sn_(x), said rods 12 having a basis 12 b        situated on said elevated regions 44 and having a length L being        at least a portion of the thickness t1 of said SWIR light        conversion layer 10; depending on the alloy composition and the        targeted quantum efficiency, the sensor material may be as thin        as 10.0 to 20.0 μm or even 1.0 to 10.0 μm. In a preferred aspect        of the embodiment the GeSn absorption layer is graded preferably        linearly with a low grading rate of about 1% up to the maximum        Sn content;    -   b4) passivating the surface of the rods 12 and filling the gaps        14 by using atomic layer deposition (ALD)—where the filling        material may preferably be SiO₂, Al₂O₃—or yttrium-doped GeO₂        [Ref. 11, Ref. 27];    -   b5) planarizing the surface on top 1 a of the rods 12 by oxide        deposition and chemical-mechanical polishing;    -   b6) providing an absorber carrier wafer on top of planarized        surface 1 a by low temperature oxide bonding;    -   b7) thinning absorber wafer II up to thickness t2. The thinning        is performed by grinding or plasma etching to a predetermined        thickness of the so far formed stack comprising said patterned        layer 40 and said SWIR light conversion layer 10. Once the stack        is thinned it forms said absorber layer II which is further        processed by the next step b8 so as to provide a bonding surface        1 c;    -   b8) providing a smooth, clean and oxide-free bonding surface 1 c        situated opposite said patterned electrical contact layer 50 by        conventional surface techniques such as chemical mechanical        polishing and wet chemical cleaning.

In an embodiment the bonding surface 1 c is passivated by a low energyhydrogen implantation in the range of 20 eV to 20 keV, as known in theart for plasma cleaning of silicon wafers to diffuse to the bondedinterface and passivate dangling bonds.

In an embodiment a doped layer 32 is provided with the same doping-typeas the charge collecting areas 24 to provide a p-n junction within theSWIR absorber II.

In an embodiment a doped layer 30 may be provided with the oppositedoping-type as the charge collecting areas 24, so as to provide a p-njunction within the CMOS wafer I.

In another embodiment the fabrication steps (b1-b7) of the absorber (II)are replaced by the following steps (b1′-b7′):

-   -   b1′) providing a second clean and oxide-free SOI substrate wafer        having either a p-type doping or n-type doping opposite to the        doping of said charge collecting areas;    -   b2′) depositing in a 2-steps RP-CVD growth process—first step at        low temperature and undoped, second step at high temperature and        doped (i.e. B₂H₆ for p-type)—a strained-relaxed Ge buffer layer        on said second silicon wafer followed by in-situ annealing;    -   b3) depositing, by a RP-CVD process, a SWIR conversion        layer—unintentionally or slightly doped—made of an        Ge_(1-x)Sn_(x) alloy composition with a Sn content x between        0.04≤x≤0.15;    -   b4′) forming a Ge contact layer by RP-CVD and doping by ions        implantation (i.e. BF₂ ⁺) followed by rapid thermal annealing        for activation;    -   b5′) providing an absorber carrier wafer on top of said contact        layer by low temperature oxide bonding;    -   b6′) thinning, to a predetermined thickness t2, the formed stack        comprising said SWIR light conversion layer so as to form said        absorber wafer;    -   b7′) providing to said absorber wafer, a smooth, clean and        oxide-free bonding surface to the side opposite of said upper        surface by conventional surface techniques such as chemical        mechanical polishing and wet chemical cleaning.

c) Bonding of the Absorber Wafer (II) and the Readout Wafer (I)

In an embodiment, in the step c) the surface 1 c is bonded to surface 1d with a wafer covalent bonding equipment—as manufactured for example byEV Group [Ref. 16], including a powerful helium plasma source to removesurface oxide—so that the SWIR detector array forms a monolithicdetector array unit 1.

After having performed steps a), b), c) an annealing step d) isperformed to realize hydrogen diffusion across the bonding interface,the annealing being performed by annealing temperatures lower than 350°C.

Additional steps are performed after the annealing step d):

-   -   e) removing the absorber carrier wafer by conventional etching        technique such as grinding, plasma etching and        chemical-mechanical polishing;    -   f) depositing on said SWIR light conversion layer 10, to the        side away from said support layer 40, a doped layer 10 c which        has a doping of the type of said patterned layer 40; for        example, a p-type contact layer may be formed by BF₂₊ ion        implantation [Ref. 11]; phosphorus (via PH₃) at 1×10¹⁹ cm⁻³ or        boron (via B2H6) at 5×10¹⁸ cm⁻³ may also be a candidate of        choice [Ref. 28];    -   g) forming contacts on top of said doped layer 10 c by        patterning and etching;    -   h) removing the readout carrier by conventional etching        techniques;    -   i) opening contacts to the readout electronics by        photolithography and dry etching;    -   j) forming a patterned electrical contact layer 50; and    -   k) providing an optical layer 100 on top of electrical contact        layer 50.

It is understood that other fabrication schemes may be implemented. Forexample there are different methods to adapt and remove carrier wafers.It is understood also that a portion of the fabrication steps may berealized in different orders. The method of fabrication using two wafersI and II is a preferred method. In a variant the realization of thelayer stack of the detector array 1 may be realized on a single carrierwafer.

Exemplary Applications

The FPA of the present invention may be used in various types ofapplications such as ground, airborne and space technology forintelligence, surveillance, military and security systems. It may alsobe used for spectroscopy, machine vision or non-invasive clinicalinvestigations such as optical coherence tomography. More precisely, theFPA of the present invention can be integrated into and used in methodsof the following fields of applications as described below.

LIDAR

System-level benefits of large FPAs are related to providing a largeinstantaneous field of view and a fully electronic selection by readingout a region of interest (FOV). Large FPAs allow monitoring of largeareas and enable key applications, such as high-resolution, wide-areaairborne persistent surveillance. The detector larger format withsmaller pixel size helps to solve the unmanned—aerial orterrestrial—vehicle (UV) automated “sense and avoid” problem. By usingan array of detectors in a FPA, the mechanical scanning needed insingle-detector systems can be avoided and because a photon-counting FPAhas the ability to digitally time stamp individual photon arrivals it isan enabler for highly sensitive light detection and ranging (“LIDAR”)imaging systems. In a LIDAR system the scene is illuminated by a shortlaser pulse, and imaged onto the FPA, where each single-photon avalanchediode measures photon arrival time, and therefore depth to thecorresponding point in the scene whereas the image is built up bycombining multiple frames.

Multi/Hyper-Spectral LIDAR Imaging

Most minerals contain distinct absorption features in the SWIR, makingthis region of the spectrum the best candidate for spectroscopicanalysis in many applications. Hydroxyl bearing minerals, sulfates, andcarbonate materials produced naturally on earth—or directly related tohuman activities such as the burning of fossil fuels and thedeforestation—are easily identified through SWIR spectroscopy.Multi/hyper-spectral LIDAR imaging can thus provide a powerful tool formapping, archaeology, earth science, glaciology, agricultural assessmentand disaster response.

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1. A short-wave infrared (SWIR) detector array (1), comprising at leastone SWIR light conversion layer (10) having a free surface forming anincident light surface (1 a) of the detector array (1), and a dopedreadout wafer (20) being either p-doped or n-doped comprising: an arrayof charge collecting areas (24) being either p-doped or n-doped chargecollecting areas (24); a readout layer (20 c) comprising an electricalcircuit (22) and defining a detector lower surface (1 b) opposite theincident light surface (1 a), said SWIR detector array being configuredto detect electromagnetic waves having a wavelength comprised between1.0 μm and 3.0 μm, wherein said SWIR detector array (1) furthercomprises a support layer (40) to its incident light side, said supportlayer (40) comprising silicon and being either p-doped or n-doped, thedoping of said support layer (40) being different with respect to thedoping of said doped readout wafer (20), said SWIR detector array (1)further comprises an intermediate layer (30) comprising a p-n junctionand a bonding interface (1 c-1 d), said intermediate layer (30) beingarranged in between said support layer (40) and said readout wafer (20),said SWIR light conversion layer (10) has a Ge1-xSnx alloy compositionand comprises, to the side away from said intermediate layer (30) adoped contact layer (10 c) having a similar doping as said support layer(40), said doped contact layer (10 c) being covered by an electricalcontact layer (50).
 2. The SWIR detector array (1) according to claim 1wherein said p-n junction is situated to the side of said support layer(40).
 3. The SWIR detector array (1) according to claim 1 wherein saidp-n junction is situated to the side of said readout layer (2 c).
 4. TheSWIR detector array (1) according to claim 1 wherein said p-n junctioncomprises said bonding interface and having a first portion situated tothe side of said support layer (40) and a second portion situated to theside of said readout layer (2 c).
 5. The SWIR detector array (1)according to claim 1 wherein said readout electrical circuit (22) is aCMOS type circuit processed in said readout layer (20 c) so as to beaccessible in said detector lower surface (1 b).
 6. The SWIR detectorarray (1) according to claim 1 wherein said light conversion layer (10)has a thickness t1, defined in a direction perpendicular to said supportlayer (40) of more than 350 nm, preferably more than 1 μm, stillpreferably more than 10 μm.
 7. The SWIR detector array (1) according toclaim 1 wherein said support layer (40) is a patterned layer andcomprises trenches (42) and elevated regions (44) to its incident lightside.
 8. The SWIR detector array (1) according to claim 7 wherein saidSWIR light conversion layer (10) is internally structured and comprisesrods (12) extending between said support layer (40) and said dopedcontact layer (10 c)
 9. The SWIR detector array (1) according to claim8, wherein said rods (12) have, defined in any cross sectionperpendicular to their length L, a <100> crystallographic orientation.10. The SWIR detector array (1) according to claim 8 wherein a greatestwidth of said rods (12), taken in any said cross section, is comprisedbetween 1 μm and 7 μm.
 11. The SWIR detector array (1) according toclaim 1 wherein said electrical contact layer (50) is a patternedelectrical contact layer (50).
 12. The SWIR detector array (1) accordingto claim 1 wherein the conversion efficiency is higher than 30%,preferably higher than 60%.
 13. The SWIR detector array (1) according toclaim 1 wherein said absorption layer (10) is realized by a LEPECVDtechnique.
 14. The SWIR detector array (1) according to claim 8comprising, to the incident light side, an optical layer (100) adaptedto direct incident light into said rods (12).
 15. The SWIR detectorarray (1) according to claim 14 wherein said optical layer (100)comprises an array of refractive microlens, or an array of diffractivemicrolenses, or an array of aspheric shaped microlenses, or an array ofmicroprisms or an array of plasmonic planar metalenses allowing formulti/hyper-spectral imaging and analysis.
 16. A method of fabricationof a SWIR detector array (1) according to claim 1 comprising the stepsof: a) fabrication of a readout wafer (I) comprising the steps of: a1)providing a first silicon wafer (20) being a low doped p or n type SOIwafer comprising a readout layer (20 c); a2) forming a readout circuit(22) in said readout layer (20 c) by a Complementary Metal OxideSemiconductor (CMOS) process; a3) realizing charge collecting areas (24)in said readout layer (20 c), said charge collecting areas (24) beingn-doped or p-doped with the same doping kind as the SOI wafer; a4)planarizing said first silicon wafer (20) to the side of readout layer(20 c); a5) adapting a readout carrier layer to said silicon wafer tothe side of said readout layer (20 c) by low temperature oxide-to-oxidebonding; a6) thinning said first silicon wafer (20) by conventionalgrinding and plasma etching techniques; a7) providing a smooth, cleanand oxide-free bonding surface (1 d) by chemical mechanical polishingand passivating, so as to provide said readout wafer (20); b)fabrication of an absorbing wafer (II) comprising the steps of: b1)providing a second silicon wafer being a SOI wafer (40) having either ap-type doping or n-type doping opposite to the doping of said chargecollecting areas (24); b2) patterning and passivating the surface ofsaid second wafer so as to form said support layer (40) comprisingtrenches (42) and elevated regions (44); b3) depositing, by a LEPECVDprocess, a SWIR conversion layer (10) made of an Ge1-xSnx alloycomposition with a Sn content x between 0.04≤x≤0.15 and so that duringthe deposition process rods (12) are formed having a composition ofGe1-xSnx, said rods (12) having a basis (12 b) situated on said elevatedregions (44) and having a length L being at least a portion of thethickness t1 of said SWIR light conversion layer (10), said rods havinga top surface (1 a) opposite to said bottom surface (12 b); b4)passivating the surface of the rods (12) and filling the gaps (14)between said rods (12); b5) planarizing the upper surface (1 a) of theSWIR conversion layer (10); b6) providing by low temperature oxide anabsorber carrier wafer on top of the planarized upper surface (1 a); b7)thinning, to a predetermined thickness t2, the formed stack comprisingsaid patterned support layer (40) and said SWIR light conversion layer(10) so as to form said absorber wafer (II); b8) providing to saidabsorber wafer (II), a smooth, clean and oxide-free bonding surface (1c) to the side opposite of said upper surface (1 a) by conventionalsurface techniques such as chemical mechanical polishing and wetchemical cleaning; c) covalently bonding surface (1 c) to surface (1 d)so as to form a bonding interface (1 c-1 d) and so that the SWIRdetector array comprises an absorber wafer (II) bonded to said readoutwafer (I), forming a monolithic detector array unit (1); d) annealingthe monolithic detector array unit (1) to realize hydrogen diffusionacross the bonding interface (1 c-1 d), the annealing being performed byannealing temperatures lower than 350° C.; e) removing said absorbercarrier wafer by conventional etching techniques; f) depositing on saidSWIR light conversion layer (10), to the side away from said readoutwafer (I) a doped layer (10 c) having a doping of the type of saidpatterned support layer (40); g) forming electrical contacts on top ofsaid doped layer (10 c); h) removing said readout carrier byconventional etching techniques; i) opening contacts to the readoutelectronics by photolithography and dry etching; j) forming a patternedor non-patterned electrical contact layer (50); and k) providing anoptical layer (100) on top of electrical contact layer (50).
 17. Amethod of fabrication of a SWIR detector array (1) according to claim 16wherein the fabrication steps b1-b8 of an absorbing wafer (II) arereplaced by the following steps b1′-b7′: b1′) providing a second cleanand oxide-free SOI substrate wafer having either a p-type doping orn-type doping opposite to the doping of said charge collecting areas;b2′) depositing by a RP-CVD process a Ge buffer layer on said secondsilicon wafer; b3) depositing, by a RP-CVD process, a SWIR conversionlayer made of an Ge1-xSnx alloy composition with a Sn content x between0.04≤x≤0.15; b4′) forming a Ge contact layer by RP-CVD and doping; b5′)providing by low temperature oxide bonding a carrier wafer on top of theplanarized upper surface; b6′) thinning, to a predetermined thicknesst2, the formed stack comprising said patterned layer and said SWIR lightconversion layer so as to form said absorber wafer; b7′) providing tosaid absorbing wafer (II) a smooth, clean and oxide-free bonding surfaceto the side opposite of said upper surface by conventional surfacetechniques such as chemical mechanical polishing and wet chemicalcleaning.
 18. The method according to claim 16 wherein the passivationof the bonding surface (1 c) is performed by a low energy hydrogenimplantation technique;
 19. The method according to claim 16 wherein adoped layer (32) is realized in said absorbing wafer (II) to the side ofsaid bonding surface (1 c), said doped layer (32) having the samedoping-type as the charge collecting areas (24) to provide a p-njunction within the absorbing wafer (II).
 20. The method of claim 16wherein a doped layer (30) is realized in said readout wafer (20), tothe side away from said readout layer (20 c), said doped layer having anopposite doping-type as the charge collecting areas (24) so as toprovide a p-n junction within the readout wafer (I).
 21. The methodaccording to claim 16, wherein in step c) said covalent bonding isrealized by a low temperature bonding technique, said low temperaturebeing lower than 300° C.
 22. An optical system, comprising said SWIRdetector array (1) according to claim 1, arranged to operate in asingle-photon counting mode.
 23. The optical system according to claim22 wherein said SWIR detector array is part of a high sensitive LIDAR.